`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   22:47:06 08/09/2015
// Design Name:   DebugUnit
// Module Name:   D:/Libraries/Documents/Ingenieria en Comp/MIPS/trunk/Final-Mips/DebugTest.v
// Project Name:  Final-Mips
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: DebugUnit
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module DebugTest;

	// Inputs
	reg clk;
	reg reset;
	reg [7:0] rx_out;
	reg rx_done;
	reg tx_done;

	// Outputs
	wire [7:0] tx_in;
	wire tx_start;
	wire run_pipe;
	wire [6:0]estado;

	// Instantiate the Unit Under Test (UUT)
	DebugUnit uut (
		.clk(clk), 
		.reset(reset), 
		.rx_out(rx_out), 
		.rx_done(rx_done), 
		.tx_done(tx_done), 
		.tx_in(tx_in), 
		.tx_start(tx_start), 
		.run_pipe(run_pipe),
		.estado(estado)
	);

	initial begin
		// Initialize Inputs
		clk = 0;
		reset = 0;
		rx_out = 0;
		rx_done = 0;
		tx_done = 0;

		// Wait 100 ns for global reset to finish
		#100;
		rx_out = 8'b 01110000;
      reset = 1;
		#1;
		reset = 0;
		rx_done = 1;
		#1;
		rx_done = 0;
		//Mandar
		#20;
		tx_done = 1;
		#2;
		tx_done = 0;
		#20;
		tx_done = 1;
		#2;
		tx_done = 0;
		#20;
		tx_done = 1;
		#2;
		tx_done = 0;
		#20;
		tx_done = 1;
		#2;
		tx_done = 0;
		
		//Dejar mandar

	end
always begin
#1; clk = ~clk;
end       
endmodule

